# Here is an example make file which should be called 'Makefile' # All lines beginning with a '#' are comments # Uncomment a line if you want it used. # Which compliler to use CC= gcc #CC= cc # Uncomment For Optimization #CFLAGS= -O2 # Uncomment For debugging #CFLAGS= -g # Libraries needed? LIBS= -lm # Leave this command as is .c.o: $(CC) -c $(CFLAGS) $(LIBS) $< # The following is an example of an executable called prog1 # which has 2 source files: src1.c and src2.c # This would be activated by typing 'make prog1' prog1: src1.o src2.o $(CC) src1.o src2.o -o prog1 # Here is prog2, which happens to share a source file with prog1 # it also has a header file that must be checked in case it has been changed prog2: header.h src1.o src3.o src4.o $(CC) src1.o src3.o src4.o -o prog2 # This one gets rid of unneeded files when you're done by typing 'make clean' # This shows how makefiles don't have to be used just for compiling clean: rm -f *.o core